Goal:
The aim of the course is to provide students with a deeper understanding of the internal structure and operating mechanisms of computers and processors, and to introduce them to the main concepts, cause-effect relationships and emerging trends. The course will introduce students to instruction-level architectures, the microarchitecture of traditional Neumann computers. The approach of the course is based on the design space concept and focuses on concrete implementation examples and trends.
Course description:
Topics: Computing models, architectures, ISA. Memory space and register space. Data types, operations, operand types, instruction formats, addressing modes. Usermanageable state attributes. RISC, CISC architectures and main features of the most common instruction level architectures. Operation execution unit, operation execution, the principle of parallel addition and multiplication. Basics of bus system, types of buses, parallel/serial buses, main features of most important parallel and serial buses (FSB, USB, PCIe, HT, QPI). DMA, and interrupt system. The concept of DRAM, types of DRAM technologies (SDRAM, DDR memory generations). Evolution of transistor technology. Levels of parallelism that can be exploited. Flynn and modern classification of processors. Data, control and resource dependencies and their main management techniques and how to maintain sequential consistency. Conveyor belt and superscalar processors. ISA extensions (MMX, SSE, …). Cache organization alternatives, cache coherence, trends, examples. Processor performance issues. Main areas of dissipation management. Thread level and process level parallel architectures.